1. Field of the Invention
The field of the invention generally relates to superscalar RISC microprocessors, more specifically, the invention relates to a CISC to RISC microprocessor instruction alignment unit and decode unit for permitting complex instructions to run on RISC-based hardware.
2. Related Art
All complex instruction set computers (CISC computers) which use variable length instructions are faced with the problem of determining the length of each instruction that is encountered in the instruction stream. Instructions are packed into memory as successive bytes of data, so that given the address of an instruction, it is possible to determine the starting address of the next instruction if you know the first instruction's length.
For a conventional processor, this length determination does not have a significant performance impact compared to other stages in the processing of an instruction stream, such as the actual execution of each instruction. As a result, fairly simple circuits are typically used. Superscalar reduced instruction set computers (RISC computers), on the other hand, can process instructions at a much higher rate, requiring instructions to be extracted from memory much more rapidly to keep up with the parallel execution of multiple instructions. This limiting factor imposed by the rate at which instructions can be extracted from memory is referred to as the Flynn Bottleneck.
The task of determining the length of each instruction and extracting that instruction from the instruction stream is performed by a function unit called an Instruction Align Unit (IAU). This block must contain decoder logic to determine the instruction length, and a shifter to align the instruction data with the decoder logic.
For the Intel 80386 microprocessor, the first byte of an instruction can have numerous implications on the overall instruction length, and may require that additional bytes be checked before the final length is known. Furthermore, the additional bytes may specify other additional bytes. It is therefore extremely difficult to quickly determine the length of the X86 instruction because the process is inherently sequential.
Based on the information provided in the i486.TM. Programmer's Reference Guide, several conclusions can be drawn regarding alignment unit present in the i486.TM.. The i486.TM.'s IAU is designed to look only at the first few bytes of the instruction. In cases where these bytes do not fully specify the length, these initial bytes are extracted and the process is repeated on the remaining bytes. Each iteration of this process requires a full cycle, so it may take several cycles, at worst case, for an instruction to be fully aligned.
Situations that require additional cycles for the i486.TM. IAU include the presence of prefixed and escaped (2 byte) opcodes. Both of these are common in i486.TM. programs. In addition, complex instructions may also comprise displacement and immediate data. The i486.TM. requires additional time to extract this data.
An example format for a CISC processor instruction is shown in FIG. 1. The example depicts the potential bytes of a variable length i486.TM. CISC instruction. The instructions are stored in memory on byte boundaries. The minimum length of an instruction is 1 byte, and the maximum length of an instruction, including prefixes, is 15 bytes. The total length of the instruction is determined by the Prefixes Opcode, ModR/M and SIB bytes.